Designing and fabricating electronic systems typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of electronic system to be manufactured, its complexity, the design team, and the fabricator or foundry that will manufacture the electronic system from a design. Typically, software and hardware “tools” verify the design at various stages of the design flow by running simulators and/or hardware emulators, or by utilizing formal techniques, allowing any errors in the design discovered during the verification process to be corrected.
Initially, a specification for a new electronic system can be transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the electronic system. With this logical design, the electronic system can be described in terms of both the exchange of signals between hardware registers and the logical operations that can be performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as System Verilog or Very high speed integrated circuit Hardware Design Language (VHDL).
The logic of the electronic system can be analyzed to confirm that it will accurately perform the functions desired for the electronic system, sometimes referred to as “functional verification.” Design verification tools can perform functional verification operations, such as simulating, emulating, and/or formally verifying the logical design. For example, when a design verification tool simulates the logical design, the design verification tool can provide transactions or sets of test vectors, for example, generated by a simulated test bench, to the simulated logical design. The design verification tools can determine how the simulated logical design responded to the transactions or test vectors, and verify, from that response, that the logical design describes circuitry to accurately perform functions.
After functional verification, the logical design can be examined for potential failures in products or processes, sometimes referred to as “functional safety validation.” Functional safety tools can perform functional safety validation by examining the logical design for potential failures and helping select remedial actions that reduce cumulative impacts of life-cycle consequences or risks from a systems failure or fault. Some types of functional safety validation can include Failure Mode and Effects Analysis (FMEA) or Failure Modes, Effects, and Diagnostic Analysis (FMEDA), which can be used in conjunction with design and manufacturing processes, and has found many applications in the automotive, aerospace, biomedical and other safety critical or security related industries. The functional safety tools typically perform functional safety validation, such as FMEA or FMEDA, by utilizing gate level timing simulations on a digital portion of the logical designs to identify critical faults in the digital portion of the logical design. When, however, the logical design includes an analog portion, the functional safety tools treat the analog portion as a black-box and cease performing functional safety validation when, for example, a fault is injected during a fault campaign that propagates into the analog portion of the logical design.